1. Technical Field
The present invention relates in general to data processing systems and in particular to buses of a multiprocessor (MP) data processing system. Still more particularly, the present invention relates to a method and system for dynamically allocating buses of a processor chip between competing external components to increase overall efficiency of the data processing system.
2. Description of the Related Art
An integrated circuit (I/C) is a device consisting of a number of connected circuit elements, such as transistors and resistors and functional combinations thereof, fabricated on a single chip of silicon crystal or other semiconductor material. In integrated circuit fabrication technology, an ever-increasing number of integrated circuit devices are being built into chips. This growing number of devices typically requires a correspondingly greater number of input/output (I/O) connections to and from the chip.
Typically, the I/O connections are conductive metal pathways, connected to the metal leads protruding from the edges of the I/C chips. These I/O connections are referred to as data buses and each set of parallel data bus is characterized by the number of bits it can transfer at a single time, equivalent to the number of parallel conducting paths (which can be thought of as wires) wired to the metal leads of an integrated circuit chip. The number of these parallel conducting paths is typically referred to as the width of the bus.
The miniaturization of integrated circuits has made it possible to pack more and more data processing power into a small volume. The increased data processing power has made it necessary to provide more metal leads (I/O connections) for each I/C chip. However, the small volume of the I/C chip (i.e., small edge surface area) has also resulted in such metal leads being tightly spaced. Consequently, on a printed circuit board utilizing modern integrated circuits, the I/O connections of the I/C chips are physically very close. Accordingly, the conductive paths, at least where they connect with individual I/O connections, are also in very close proximity to each other.
It can be seen that merely from the standpoint of spatial dimensions, there has to be an upper limit of the amount of conductors that can be placed in parallel. However, long before that spatial limit is reached, electromagnetic interference (e.g., coupling effects) between such parallel conductors starts to impinge upon the effectiveness of data transmission, since at some point such interference effects make the placing of more conductors in parallel impractical.
While the limit of number of conductors practicably connected in parallel is rapidly approaching, the processing power of integrated circuits continues to increase and the volume of the I/C chip continues to shrink. Also, each advance in integrated circuit technology typically requires an increase in bus width to transmit the processed data on and off chip; that is, data bus requirements of integrated circuits have gone from 16 to 32 to 64 to 128 line buses, with some of the more recent advances requiring 256 lines or higher, with no end to bus requirements in sight.
One common I/C chip is the processor chip utilized within a data processing system. Current designs of data processing systems involve coupling together several of these processor chips to create multi-processor data processing systems (or symmetric multiprocessor (SMP) data processing systems). In conventional symmetric multiprocessor (SMP) data processing systems, all of the processors are generally identical. The processors all utilize common instruction sets and communication protocols, have similar hardware architectures, and are generally provided with similar memory hierarchies. For example, a conventional SMP data processing system may comprise a system memory, a plurality of processing elements that each include a processor and one or more levels of cache memory and a system bus coupling the processing elements to each other and to the system memory.
Traditionally data processing systems were designed with single processor chips having one or more central processing units (CPU). In these traditional single chip data processing systems, all bus interfaces were utilized by memory, other caches, and input/output (I/O) devices. With the fast growth of multi-processor data processing systems and the corresponding need for additional processing power, new multi-chip modules comprising multiple processor chips were developed. Building larger scalable SMPs requires the ability to hook up multiple numbers of these chips utilizing the bus interface. In order to accommodate these other devices, the size of the memory bus interface was reduced and these bus interfaces were utilized for the other external components, particularly other SMPs. In these multi-chip modules, certain of the buses traditionally dedicated to memory processes such as data transfer have been dedicated to connecting other processor chips (i.e., processors located on other chips). With the allocation of memory buses to these chips due in part to limitations in the size of the chip (i.e., it is impossible to add new buses to the already compressed design of the chip), current data processing systems processor chips operate with a smaller bus bandwidth made available to the memory processes.
With the traditional configuration of a SMP, the chip""s I/Os are utilized by all external components connected to the system bus which communicate with the processor. This is referred to as a tri-state topology. Each external component can send and receive information via the system bus and chip I/Os. However, this topology works well only in the slower processors. As previously mentioned, the processor speed is steadily increasing, resulting in each component requiring wider and dedicated bandwidth. Unfortunately, tri-state topology systems are unable to efficiently handle the greater demands on the buses because they are unable to scale at the same level as the processors. These higher frequency processors, such as those operating at 1 Ghz, have necessitated the development of a point-to-point topology, wherein the buses are separately and distinctly allocated to a specific external component. In this topology, some I/Os are utilized for direct connection to memory, other pins for additional processors in multi-processor chip systems, and still others for I/O components. Thus, in point-to-point topology, the I/O pins are predetermined/pre-allocated for connection to a specific external component. Notably, the I/Os for memory and those for other processors are utilized as buses which are distinct and separate.
Typically, processors and higher level caches are located on a processor chip, which is designed with a plurality of buses extending off of the edges of the chip. These chips in turn have a set of dedicated buses through which the processors communicate to external components such as memory, input/output (I/O) devices and other processors. Traditionally, the allocation of these buses is predefined during the design and development stage. In a distributed memory system, for example, a set number of chip I/Os are designed for memory access while another set of chip I/Os are designed for connection to the other external components, such as other processors in a multi-chip configuration.
These bus interfaces connecting other chips are interchangeably referred to as scalability ports, as they allow the processor to be expanded to include other processors in a multi-processor module. In the standard SMP design, one bus on the processor chip is specifically allocated to a one-to-eight-way symmetric multiprocessor (SMP). In another common design, a second bus is allocated to accommodate an eight-to-thirty two (8-32)-way SMP. This 8-32-way bus may be infrequently utilized since most systems are typically 1-8 way SMPs.
Thus current processor chips are designed with fixed dedicated buses which handle either memory transactions or SMP processor transactions. Often, changes in demands for bandwidths occur and there are times when the memory requires more bandwidth (i.e., a larger number of available buses than is available in a fixed-configuration bus allocation) while the SMP requires even less bandwidth than is provided in a fixed-allocation chip configuration. Alternatively, the memory may require less bandwith while the SMP requires more bandwidth. This condition becomes more frequent today given the bursty nature of traffic (data and other workloads) due in part to the characteristics of Internet based and other similar applications. Thus there are peaks and valleys in the workload and the corresponding requests for bandwidth from the memory and other processors. Presently there is no way of determining the needs of the system with respect to increased bandwidth to the memory buses versus bandwidth use by the SMP buses. Neither is there any method, system, or processor design which allocates buses of a chip based on the actual needs of the overall system. Efficiency in the processor and overall system is lost due to the rigidity of present chip designs.
The present invention thus recognizes that it would be desirable to have a data processing system which allocates processor chip I/Os to memory components, I/O components, and other processor chips based on overall system (or processor) needs. It is also desirable to have a method and system for dynamically configuring a bus allocation of a processor chip utilizing hardware/and or software allocation methods, (i.e., static and dynamic allocation mechanisms). It would be further desirable to allocate processor chip bus bandwidth in such a manner that the efficiency of the processor and the overall data processing system is enhanced.
It is therefore one object of the present invention to provide an improved data processing system.
It is another object of the present invention to provide an improved method and system for bus allocation on a multiprocessor (MP) data processing system;.
It is yet another object of the present invention to provide a method and system for dynamically allocating buses of a MP chip between competing external components to increase overall efficiency of the data processing system.
The foregoing objects are achieved as is now described. A data processing system with configurable processor chip buses is described. The processor chip is designed with a plurality of extended buses (I/Os) of which a number may be dynamically allocated to memory (or other component) and the remainder may be allocated to other SMPs. A number of the buses are designed as configurable/floating buses. The processor chip allows for the dynamic allocation of these configurable buses to either component, based on the present needs of the system to improved overall efficiency.
In one embodiment, a single bus is hardware configurable. When the workload (or bandwidth demand) of the memory increases beyond the allocated buses, the configurable bus is dynamically allocated to memory via hardware manipulation. In another preferred embodiment, the configurable buses are dynamically allocated based on a software manipulation of a bus allocation unit.
The above as well as additional objects, features, and advantages of an illustrative embodiment will become apparent in the following detailed written description.